| Autor: |
Xing-hua, He, Cong, Zhang, Yong-liang, Zhang, Huan-zhang, Lu |
| Zdroj: |
Advanced Techniques in Computing Sciences & Software Engineering; 2010, p191-196, 6p |
| Abstrakt: |
The single event effects (SEE) characteristic and hardening techniques of CMOS SRAM with sub-micron feature size are studied in the paper. After introducing the relationship SEE with the structure of memory cell, the rate of read-write, the feature sizes and the power supply, the SEE hardening techniques for the COMS SRAM are given from tow aspect: device-level hardening techniques and system-level hardening techniques. Finally, an error detection and correction (EDAC) design based on high reliability anti-fused FPGA is presented, this design has special real-time performance and high reliability, and has been adopted in a space-bone integrated processor platform, which works well in all kinds of environmental experiments. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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