| Autor: |
Duranton, Marc, Hoogerbrugge, Jan, Al-kadi, Ghiath, Guntur, Surendra, Terechko, Andrei |
| Zdroj: |
Processor & System-on-chip Simulation; 2010, p259-275, 17p |
| Abstrakt: |
Multicore architectures provide scalable performance with a hardware design effort lower than for a single core processor with similar performance. This chapter presents a design methodology and an embedded multicore architecture focusing on boosting performance density and reducing the software design complexity. The methodology is based on a predictive formula computing performance of heterogeneous multicores, which allows drastic pruning of the design space for few accurate simulations. Using this design space exploration methodology for high definition and quad high definition H.264 video decoding, the resulting areas for a multicore system in CMOS 45 nm are 2.5 and 8.6 mm2, respectively. These results show that heterogeneous chip multiprocessors are cost-effective for embedded applications. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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