| Autor: |
Bekiaris, Dimitris, Papanikolaou, Antonis, Papameletis, Christos, Soudris, Dimitrios, Economakos, George, Pekmestzi, Kiamal |
| Zdroj: |
Integrated Circuit & System Design. Power & Timing Modeling, Optimization & Simulation (9783642177514); 2011, p73-83, 11p |
| Abstrakt: |
The shrinking of interconnect width and thickness, due to technology scaling, along with the integration of low-k dielectrics, reveal novel reliability wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependent Dielectric Breakdown (TDDB) between wires of the same layer, considering temperature variations. The proposed framework is evaluated on a Leon3 MP-SoC design, implemented at a 45nm CMOS technology. The results evaluate the system΄s performance drift due to TDDB, considering different physical implementation scenarios. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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