| Autor: |
Jones, Gary, Tandon, Sanjay |
| Zdroj: |
Journal of Electronic Materials; Jan1990, Vol. 19 Issue 1, p89-93, 5p |
| Abstrakt: |
Interconnections between semiconductor devices in integrated circuits continue to present difficult problems in the tradeoffs between RC time constants, production worthiness, reliability, structural complexity, and compactibility for any single technology. A process and structure has been demonstrated for integrated circuit interconnections which uses a conformai tungsten layer deposited by chemical vapor deposition to provide step coverage into via holes of variable height. The film is then patterned with a via interconnect pattern designed for liftoff processing, layers of chromium copper and chromium are then deposited insitu on the wafers by way of evaporation. The undesired material is lifted off in a solvent process and the resulting metal pattern is used as the mask for the reactive ion etching of CVD tungsten. This combination of materials and process allows for high conductivity reliable interconnections with negligable step coverage problems. Processing and test information will be presented in the paper. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
Full text from SpringerLink