| Abstrakt: |
A hybrid silicon wafer-scale multi-chip packaging design was chosen as the basis for a high performance, high power dissipation vehicle suitable for VLSI/ULSI applications. The package supports 25 chips (l x l cm), each capable of dissipating as much as 40 W. The heat generated by the chips is removed by water channels in the underlying structure. Deep- (about 1000 μm), and shallow- (about 100 μm. deep), channel designs, with a water flow rate of 499 cc/sec, and 39 cc/sec, respectively, have been analyzed. Both designs are capable of keeping circuit temperature rise small, while maintaining a uniform chip temperature. The temperature distribution of the thermal module was obtained by solving the 2-D heat conduction equation for isolated heat sources (the chips), and heat sinks (the water channels). Assuming that each of the 25 chips dissipates 40 W/cm, and heat is removed only via water flow, the maximum chip tempertaure (t which occurs at the center of a chip) rise relative to inlet water temperature is 11.4° C, and 19.0° C for the deep, and shallow designs, respectively. The maximum t variation between chips on the module (the same as the water temperature rise), for the cases analyzed, is 0.5° C for the deep-channel design, and 6° C for the shallow-channel design (calculated at 25° C inlet water temperature, and an optimum flow rate). For the extremely-uneven powered case (all chips except one at the inlet end are powered at 40 W/chip), the maximum temperature increases between inlet water temperature and chip temperature, t , remain relatively the same, but the maximum t variations between chips on the module increase to 11.4° C, and 19° C for the deep, and shallow designs, respectively, as might be expected. The temperature variation on a powered chip is less than 3° C for both the deep- and shallow-channel designs. [ABSTRACT FROM AUTHOR] |
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