| Autor: |
Xu, Hongtao, Palaskas, Yorgos, Ravi, Ashoke, Sajadieh, Masoud, El-Tanani, Mohammed A., Soumyanath, Krishnamurthy |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jun2011, Vol. 46 Issue 7, p1596-1605, 10p |
| Abstrakt: |
A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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