| Autor: |
Zhaozhi Li, Sangil Lee, Lewis, Brian J., Houston, Paul N., Baldwin, Daniel F., Stout, Eugene A., Tessier, Theodore G., Evans, John L. |
| Předmět: |
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| Zdroj: |
Advancing Microelectronics; Jul2010, Vol. 37 Issue 4, p20-25, 6p, 7 Color Photographs, 5 Black and White Photographs, 4 Diagrams, 2 Charts, 3 Graphs |
| Abstrakt: |
The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. No flow underfill is of a special interest for the wafer level flip chip assembly as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would be otherwise necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction and the yield improvement. Also, different no flow underfill candidates were investigated for the best performing processing material. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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