High performance low power array multiplier using temporal tiling.
| Autor: | Mahant-Shetti, S.S., Balsara, P.T., Lemonds, C. |
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| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Mar1999, Vol. 7 Issue 1, p121-124, 4p |
| Databáze: | Complementary Index |
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