A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
| Autor: | Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo |
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| Zdroj: | IEEE Journal of Solid-State Circuits; May2002, Vol. 37 Issue 5, p612-623, 12p |
| Databáze: | Complementary Index |
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