A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
| Autor: | Takai, Y., Fujita, M., Nagata, K., Isa, S., Nakazawa, S., Hirobe, A., Ohkubo, H., Sakao, M., Horiba, S., Fukase, T., Takaishi, Y., Matsuo, M., Komuro, M., Uchida, T., Sakoh, T., Saino, K., Uchiyama, S., Takada, Y., Sekine, J., Nakanishi, N. |
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| Zdroj: | IEEE Journal of Solid-State Circuits; Feb2000, Vol. 35 Issue 2, p149-162, 14p |
| Databáze: | Complementary Index |
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