A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures.

Autor: Benso, Alfredo, Cataldo, Silvia, Chiusano, Silvia, Prinetto, Paolo, Zorian, Yervant
Zdroj: Journal of Electronic Testing; Jun2000, Vol. 16 Issue 3, p179-184, 6p
Abstrakt: This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip. [ABSTRACT FROM AUTHOR]
Databáze: Complementary Index
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