| Autor: |
Sin, S.-W., Seng-Pan, U., Martins, R. P. |
| Předmět: |
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| Zdroj: |
IET Circuits, Devices & Systems (Institution of Engineering & Technology); Jan2010, Vol. 4 Issue 1, p1-13, 13p, 1 Black and White Photograph, 8 Diagrams, 3 Charts, 4 Graphs |
| Abstrakt: |
A low-voltage 1.2-V, 10-bit, 60–360 MS/s six channels time-interleaved reset-opamp pipelined ADC is designed and implemented in a 0.18-µm CMOS (VTHN/VTHP=0.63 V/-0.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-VT options, the proposed ADC employs low-voltage resistive-demultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60–360 MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a differential non-linearity (DNL)/integral non-linearity (INL) better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm2. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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