| Autor: |
Touba, Nur A., McCluskey, Edward J. |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Apr2001, Vol. 20 Issue 4, p545, 11p, 2 Black and White Photographs, 2 Charts, 6 Graphs |
| Abstrakt: |
Features a study which proposed a low-overhead scheme for achieving complete fault coverage during the built-in self test of circuits with scan. Process in digital design and logic circuit systems; Details on the random-pattern resistant faults in random pattern sequence; Methodology and discussion. |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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