| Autor: |
Yousry, Ramy, Hegazi, Emad, Ragai, Hani F. |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Oct2008, Vol. 55 Issue 9, p2469-2482, 14p, 3 Black and White Photographs, 18 Diagrams, 1 Chart, 9 Graphs |
| Abstrakt: |
We present a wideband architecture for ΔΣ modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate over sampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-μm CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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