| Autor: |
De Micheli, Giovanni, Mir, Salvador, Reis, Ricardo, Mitra, Subhasish, Zhang, Ming, Seifert, Norbert, Mak, T. M., Kim, Kee Sup |
| Zdroj: |
VLSI-SoC: Research Trends in VLSI & Systems on Chip; 2008, p143-156, 14p |
| Abstrakt: |
This paper presents an overview of the Built-In Soft Error Resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 7-11% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several classical error-detection techniques introduce 40-100% power, performance and area overheads, and require significant efforts in designing and validating corresponding recovery mechanisms. Design trade-offs associated with the BISER technique and other existing soft error protection techniques are also analyzed. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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