| Autor: |
Hutchison, David, Kanade, Takeo, Kittler, Josef, Kleinberg, Jon M., Mattern, Friedemann, Mitchell, John C., Naor, Moni, Nierstrasz, Oscar, Pandu Rangan, C., Steffen, Bernhard, Sudan, Madhu, Terzopoulos, Demetri, Tygar, Doug, Vardi, Moshe Y., Weikum, Gerhard, Keqiu Li, Jesshope, Chris, Hai Jin, Gaudiot, Jean-Luc, Rong Ji |
| Zdroj: |
Network & Parallel Computing (9783540747833); 2007, p476-485, 10p |
| Abstrakt: |
The multiply clock domain (MCD) technique is a novel technique to compromising between synchronous systems and asynchronous systems to reduce the power. However, most present studies of MCD are based on superscalar architectures. In this paper, MCDE, a MCD technique based on explicitly parallel instruction computing (EPIC) architecture is designed and implemented to reduce the power of clock distribution network. In addition, a series of experiments have been done to evaluate it. The result of the experiments show that, using a MCDE clock network microarchitecture with a fine-grained adaptive dynamic adjustment algorithm, can effectively decrease the microprocessor power by 40%, compared with the original EPIC clock network microarchitecture. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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