| Autor: |
Noori, Atif M., Balseanu, Mihaela, Boelen, Pieter, Cockburn, Andrew, Demuynck, Steven, Felch, Susan, Gandikota, Srinivas, Gelatos, A. Jerry, Khandelwal, Amit, Kittl, Jorge A., Lauwers, Anne, Wen-Chin Lee, Jianxin Lei, Mandrekar, Tushar, Schreutelkamp, Robert, Shah, Kavita, Thompson, Scott E., Verheyen, Peter, Ching-Ya Wang, Li-Qun Xia |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Electron Devices; May2008, Vol. 55 Issue 5, p1259-1264, 6p, 1 Diagram, 6 Graphs |
| Abstrakt: |
Manufacturable processes to reduce both channel and external resistances (RExt) in CMOS devices are described. Simulations show that RExt will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiNx liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance (Rc) is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces Rc by > 35% as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a ~10% increase in the PMOS drive current. By implementing a two-step anneal process (spike + laser), the source/drain-extension resistance can be reduced by 20%. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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