Autor: |
Maesoon Im, Jin-Woo Han, Hyunjin Lee, Lee-Eun Yu, Sungho Kim, Chang-Hoon Kim, Sang Cheol Jeon, Kwang Hee Kim, Gi Sung Lee, Jae Sub Oh, Yun Chang Park, Hee Mok Lee, Yang-Kyu Choi |
Předmět: |
|
Zdroj: |
IEEE Electron Device Letters; Jan2008, Vol. 29 Issue 1, p102-105, 4p, 1 Chart, 1 Graph |
Abstrakt: |
An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
Externí odkaz: |
|