Defect Passivation With Fluorine and Interface Engineering for Hf-Based High-κ/Metal Gate Stack Device Reliability and Performance Enhancement.

Autor:	Hsing-Huang Tseng, Tobin, Philip J., Kalpat, Sriram, Schaeffer, Jamie K., Ramón, Michael E., Fonseca, Leonardo R. C., Jiang, Zhixiong X., Hegde, R. I., Triyoso, Dina H., Semavedam, S.
Předmět:	INTEGRATED circuit passivation STRESS relieving (Materials) VOLTAGE regulators PASSIVITY (Chemistry) RESIDUAL stresses DEFORMATIONS (Mechanics) FLUORINE INTERFACE circuits FAULT tolerance (Engineering)
Zdroj:	IEEE Transactions on Electron Devices; Dec2007, Vol. 54 Issue 12, p3267-3275, 9p, 7 Black and White Photographs, 24 Graphs
Abstrakt:	Using a fluorinated high-κ/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-κ deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-κ is a concern. The novel fluorinated Ta∞ Cy/HtZrO∞/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative- bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon. [ABSTRACT FROM AUTHOR]
Databáze:	Complementary Index
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