Autor: |
Shringarpure, Rahul, Venugopal, Sameer, Zi Li, Clark, Lawrence T., Allee, David R., Bawolek, Edward, Toy, Daniel |
Předmět: |
|
Zdroj: |
IEEE Transactions on Electron Devices; Jul2007, Vol. 54 Issue 7, p1781-1783, 3p, 1 Diagram, 1 Chart, 1 Graph |
Abstrakt: |
This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
Externí odkaz: |
|