| Autor: |
Heydari, Payam, Mohanavelu, Ravindran |
| Zdroj: |
IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Dec2006, Vol. 53 Issue 12, p1358-1352, 5p, 3 Diagrams, 1 Chart, 7 Graphs |
| Abstrakt: |
This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-µm SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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