Autor:	Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang
Předmět:	SPARSE matrices ELECTRIC circuits ELECTRIC wiring COMPLEMENTARY metal oxide semiconductors ELECTRIC power
Zdroj:	Journal of Computer Science & Technology (10009000); Jan2007, Vol. 22 Issue 1, p25-27, 3p
Abstrakt:	Abstract??This paper presents an optimized 64-bit parallel adder. Sparse-tree architecture enables low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18?m CMOS process. It achieves the goal of higher speed and lower power. [ABSTRACT FROM AUTHOR]
Databáze:	Complementary Index
Externí odkaz:	Zobrazit plný text záznamu Full text from SpringerLink