| Autor: |
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Jan2007, Vol. 42 Issue 1, p170-182, 13p, 20 Diagrams, 3 Charts |
| Abstrakt: |
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on 11D1080 video (1920 × 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 µm CMOS technology, the proposed design occupies 2.9 × 2.9 mm² silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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