LOW-POWER DESIGN APPROACH OF 11F04 250-KBYTE. EMBEDDED SHAM FOR THE SYNERGISTIC PROCESSOR ELEMENT OF A CELL PROCESSOR.

Autor: Asano, Tory, Silberman, Joel, Dhong, Sang H., Takahashi, Osamu, White, Michael, Cottier, Scott, Nakazato, Takaaki, Kawasumi, Atsushi, Yoshihara, Hiroshi
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Zdroj: IEEE Micro; Sep/Oct2005, Vol. 25 Issue 5, p30-38, 9p
Abstrakt: The article discusses low-level design issues related to achieving a high-performance SRAM design at low power. SRAM avoids risky techniques because of its intended high-volume production. SRAM cells consist entirely of high-14 devices. SRAM uses dynamic circuits only when absolutely necessary to achieve the delay objectives. The dynamic node is designed to minimize capacitance because a large dynamic node requires large precharge circuits. The design uses spaced wire as much as possible, reordering wires as necessary. Avoiding hostile signal relationships helps minimize delay and power. Efficient floor plan and wire design always help both performance and power. In deep-submicron technology, signal-to-noise margin is not enough to cause stability issues. Even if the cell is stable enough, it might still have write or read performance problems. In actual hardware, single-cell fails (SCFs) dominate. AC test shows more SCFs than DC test. Conventional design uses redundancy to fix manufacturing defects, and some performance penalty used to be acceptable, assuming that a design scarcely used redundancy.
Databáze: Complementary Index