| Autor: |
Hillard, Robert J., Benjamin, Mark C., Brown, George A. |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2005, Vol. 788 Issue 1, p287-296, 10p |
| Abstrakt: |
Electrical metrology has been highly valuable in the development and control of MOS Device Fabrication Processes. The need for electrical measurements will continue for sub-100 nm Technology. For example, methods developed to monitor process contamination such as mobile ion density and iron were required for larger technology nodes. Current and future technologies require accurate and precise determinations of the gate dielectric properties Equivalent Oxide Thickness (EOT), leakage current (ILK) and Interface Trap Density (Dit). Traditional methods for determining these parameters are challenged by thinner gate dielectrics and shallower junctions. Improved hardware, data acquisition and analysis are required. In this paper, recent developments necessary for the electrical characterization of sub-100 nm MOS structures are discussed. The three major areas of concern in MOS device engineering are covered; gate engineering, channel engineering and source-drain extension engineering. © 2005 American Institute of Physics [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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