| Autor: |
MISHRA, VISHWAS, AKASHE, SHYAM, MISHRA, DIVYA |
| Zdroj: |
Journal of Active & Passive Electronic Devices; 2024, Vol. 18 Issue 2, p91-103, 13p |
| Abstrakt: |
In this present scenario, the aggressive scaling affects the working of electronic appliances mostly in Integrated Circuits (IC's) that contains memory which covers almost 65% of that circuitry due to high demand of storage by users the memory size almost covers the 70-80% of the System on Chip (SoC) in International Technology Roadmap for Semiconductor (ITRS) 2015. When we are working on the single bit of any memory cell then that time, the power consumption is miniature level that we can calculate in Pico-watt (pW) or Nano-watt (nW) but as we moves towards the array of memory or kilo byte (kB) then the consumption also increases and reached in micro-watt level. In VLSI industries at lower supply voltage, we can compromise with the technology but we cannot negotiate with the parameters variations mostly in stability, delay and power consumption. The key points are the lowest feature sizes (W/L ratio), lowest power consumption, reduced costs and good stability for designing of any electronic component. This paper emphasis on designing of 4X4 array and single bit of FinFET which based on 10T SRAM Cell and comparison has been done with the CMOS based designing. By 4x4 arrays we can compare the parameters variation from 1 bit to 16 bits and calculated the power consumption, stability and delay at different operating point 0.5, 0.6, 0.7 and 1V and operating mode of write and read mode. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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