| Autor: |
Lee, Wai-Kong, Seo, Seog Chung, Seo, Hwajeong, Kim, Dong Cheon, Hwang, Seong Oun |
| Zdroj: |
IEEE Embedded Systems Letters; Dec2024, Vol. 16 Issue 4, p481-484, 4p |
| Abstrakt: |
The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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