| Autor: |
Pengfei Zhang, Der, Lawrence, Dawei Guo, Sever, Isaac, Bourdi, Taoufik, Lam, Christopher, Zolfaghari, Alireza, Chen, Jess, Gambetta, Douglas, Baohong Cheng, Gowder, Sujatha, Hart, Siegfried, Lam Huynh, Thai Nguyen, Razavi, Behzad |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Sep2005, Vol. 40 Issue 9, p1932-1939, 8p, 8 Diagrams, 6 Graphs |
| Abstrakt: |
This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54°/1.1° for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5 dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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