| Autor: |
Dabbagh, Arsalan, Karamimanesh, Mehrzad, Hassanli, Kourosh, Abiri, Ebrahim |
| Zdroj: |
Journal of Supercomputing; Jan2025, Vol. 81 Issue 1, p1-26, 26p |
| Abstrakt: |
The shortcomings of traditional von Neumann architectures have become more evident in the artificial intelligence (AI) and machine learning (ML) era. The continuous data flow between memory and processing units, combined with the demand for frequent and extensive processing, has led to decreased throughput and increased power consumption. Recent research explores the use of low-precision values like binary and ternary for AI hardware implementation algorithms as a potential solution. In this paper, a Charge-domain multiply-and-accumulate (CD-MAC) operation using a mixed-signal SRAM-based computing-in-memory accelerator is introduced, which performs binary/ternary processes to expedite ML and AI execution. These binary/ternary MAC operations are performed in situ through a combination of discharge-based and charge-sharing analog computing techniques. The proposed CD-MAC is simulated in 15-nm FinFET technology and demonstrates a 1.7x-5.8x improvement in TOPS/W compared to previous low-precision accelerators, consuming 1.63 W. It achieved an energy efficiency of 697 TOPS/W and a speed of 65 GOPS for ternary MAC operations, with 88% test accuracy in a recognition task involving random digit and letter images. The use of clustering techniques in the cell array enhances the accelerator’s accuracy and compatibility for various MAC operations, leading to reduced power consumption during computation. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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