| Autor: |
Rashtian, Mohammad, Shahpasandi, Mahdi |
| Předmět: |
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| Zdroj: |
AUT Journal of Electrical Engineering; 2024, Vol. 56 Issue 3, p439-452, 14p |
| Abstrakt: |
This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (VREF) to the power supply variations. For low-power operation, all transistors operate in the subthreshold region. The design's performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at Vdd = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with Vdd = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σVREF/μVREF) = 2.3% is obtained. This design's average line sensitivity (LS) is 0.072%/V (Vdd = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively. The output noise at the frequency of 1 KHz is obtained as 167.34 nV/√ Hz. The proposed VR occupies a small active area of 513.5 μm2. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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