| Abstrakt: |
This paper describes a 255-bit modular multiplier used as the core functional block for special curves cryptographic processor. Vectorized modular multiplication based on radix-225.5 representation (R25.5_VMM) was applied, and column-wise parallel processing of VMM table was proposed for efficient hardware implementation of R25.5_VMM. As a result, the number of adder operands and carry bits in the carry chain were reduced, minimizing critical path delay. The designed modular multiplier consists of one-dimensional array of 10 processing elements, each of which consists of a 32-bit x 26-bit multiplier, a 58-bit adder, and a register. The hardware operation of the modular multiplier was verified using a Zynq-7 FPGA device, and implemented using 4,715 LUTs, 893 flip-flops, and 20 DSP blocks. It was evaluated that a 255-bit modular multiplication took 11 clock cycles, resulting in a 13.88 million modular multiplications per second at a maximum operating clock frequency of 152 MHz. [ABSTRACT FROM AUTHOR] |
