| Abstrakt: |
This paper aims to develop a robust (1+PD)-PID cascade controller for the frequency stabilization of a multi-area Interconnected Power System (IPS). The operational performance of the proposed controller is studied by introducing a Step Load Disturbance (SLD) of 10% in area 1 of the considered power system model. For fine-tuning the proposed controller, the Butterfly Optimization Algorithm (BFOA) is employed. The superior performance of the proposed controller is validated against other controllers available in the literature. Furthermore, to enhance power system performance, a High-Voltage DC (HVDC) line is implemented in the test system model. The simulation results confirm the improvement in system performance with the incorporation of the HVDC line. To assess the robustness of the proposed controller, a sensitivity test is conducted, which validates its robustness. [ABSTRACT FROM AUTHOR] |
