Autor: |
Haijie Chen, Ziyao Bian, Tao Liu, Jielei Xie, Jingyu Wu, Yaojian Lin, Choon Heung Lee |
Předmět: |
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Zdroj: |
Advancing Microelectronics; 2024, Vol. 51 Issue 4, p26-31, 6p |
Abstrakt: |
The concept of a chiplet has been proposed in the post Moore era. How to layout multiple chips with different processes and sizes in the package structure is a coming problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with significant CTE mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect normal operations of the production line. Stress accumulation on a specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis (FEA) can be applied to evaluate various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
Externí odkaz: |
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