| Autor: |
Mejmaa, Bilal, Marktani, Malika Alami, Akharraz, Ismail, Ahaitouf, Abdelaziz |
| Předmět: |
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| Zdroj: |
Computers (2073-431X); Aug2024, Vol. 13 Issue 8, p195, 12p |
| Abstrakt: |
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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