| Autor: |
Neerugatti, Kusuma, Pakala, Venugopal |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2024, Vol. 3044 Issue 1, p1-7, 7p |
| Abstrakt: |
Modern 5G base station terminals require high-performance frequency synthesizers (FS). The Phase Frequency Detector (PFD) has been one of the essential building blocks for any phase-locked loop (PLL)-based FS. The paper describes a PFDdesign with low power and less dead-zone. This work investigates the Current Mode Logic (CML) PFD design technique for limiting jitter and phase noise. The proposed design overcame the dead-zone problem by optimizing CML_PFD to delay cells and pass transistor logic. The resultant analysis shows a power consumption of less than 60 µW at the maximum 3.8 GHz frequency, eliminating the dead-zone problem. The proposed architecture has been developed for the Factional-N FS design for the sub-6GHz frequency band, and it has been implemented in the UMC 180nm process. The study was conducted using the Cadence tool-EDAwork environment to attain linearity. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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