FPGA-based tiling scheme and on-chip memory scheduling scheme for multi-branch semantic segmentation neural network accelerator.
| Autor: | Li, Hui, He, Pengyu, Lu, Shengli |
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| Zdroj: | Journal of Physics: Conference Series; 2024, Vol. 2807 Issue 1, p1-12, 12p |
| Databáze: | Complementary Index |
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