Power-aware partitioning and test time reduction for 3D-SoC.

Autor: Banerjee, Sabyasachee, Majumder, Subhashis, Bhattacharya, Bhargab B., Das, Debesh K.
Zdroj: Innovations in Systems & Software Engineering; Sep2024, Vol. 20 Issue 3, p485-498, 14p
Abstrakt: The technology of 3D-ICs has been widely used in designing core-based systems-on-chip (SoC), which comprises vertical stacking of multiple silicon and metal layers, interconnected using through-silicon vias (TSV). Testing of the embedded cores in such a device not only requires a specially designed test access mechanism (TAM) but proper scheduling of tests in order to minimize the overall test time. Because of the design constraints on the number of TSVs (TSV count), the accessibility to different layers is often compromised, leading to an increase in test time. Also, the energy consumed during the execution of tests mandates the deployment of thermal vias to facilitate heat dissipation from various layers. In this manuscript, a scheduling-based test time reduction scheme for post-bond testing of 3D SoCs is proposed, which aims to reduce the test time under the constraints on TAM width, TSV count, and power budget. We address this problem by proposing a new partitioning method for assigning the layers to cores satisfying these optimization criteria. The proposed method has been tested on several ITC-02 benchmarks, and results show a notable reduction in test time for most of the cases compared to previous work. [ABSTRACT FROM AUTHOR]
Databáze: Complementary Index
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