| Autor: |
Bhowmik, Sabarni, Majumder, Tanmoy, Bhattacharjee, Abhishek |
| Předmět: |
|
| Zdroj: |
Journal of VLSI Circuits & Systems (JVCS); 2024, Vol. 6 Issue 1, p1-6, 6p |
| Abstrakt: |
Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL) approach is proposed as an efficient power reduction technique in this work to reduce the overall power consumption of any VLSI circuit. One of the most significant area of research in today's VLSI domain is power reduction. By using a complementary phase-shifted voltage source, we can minimize the charging-discharging of the load capacitor in each clock pulse, which plays a vital role in reducing the circuits' dynamic power consumption. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
|
