| Autor: |
Tagami, Hitoyuki, Kobayashi, Tatsuya, Miyata, Yoshikuni, Ouchi, Kazuhide, Sawada, Kazushige, Kubo, Kazuo, Kuno, Katsuhiko, Yoshida, Hideo, Shimizu, Katsuhiro, Mizuochi, Takashi, Motoshima, Kuniaki |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Aug2005, Vol. 40 Issue 8, p1695-1705, 11p, 11 Black and White Photographs, 8 Diagrams, 2 Charts, 6 Graphs |
| Abstrakt: |
We describe the design concept and performance of a 3-bit soft-decision IC, which opens a vista for new terabit-capacity optical communication systems by dramatically improving the capability of forward error correction (FEC). The proposed soft-decision IC is composed of five functional blocks, i.e., a soft-decider, an error filter, a 3-bit encoder, a 3:48 de-multiplexer, and a clock recovery circuit. The biggest challenge was the soft-decision block regenerating the common data using seven deciders with separate thresholds. We employed a novel SiGe BiCMOS process and a custom BGA package made from low-temperature co-fired ceramics to achieve a high sensitivity of 20 mVpp with a wide phase margin of 270° for 12.4-Gb/s nonreturn-to-zero (NRZ) data signals. The error filter and the 3-bit encoder, which are incorporated in the IC, prevent the degradation of the FEC performance due to signal noise or fluctuations. The 3:48 de-multiplexer provides an accessible interface with the FEC encoder/decoder LSI. The clock recovery circuit, based on a phase-locked-loop technology, fulfilled the jitter tolerance requirements corresponding to ITU-T G.825, even for 55% duty cycle optical return-to-zero (RZ) signals. The 3-bit soft-decision IC, in cooperation with a block turbo encoder/decoder, achieved a record net coding gain of 10.1 dB with 24.6% redundancy, which is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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