| Autor: |
Nair, Arun S., Patil, Geeta, Agarwal, Archit, Pai, Aboli V., Raveendran, Biju K., Punnekkat, Sasikumar |
| Předmět: |
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| Zdroj: |
International Journal of Parallel, Emergent & Distributed Systems; May2024, Vol. 39 Issue 3, p317-352, 36p |
| Abstrakt: |
CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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