Autor: |
Dutt, Arya, Tiwari, Sanjana, Joshi, Mayuresh, Nigam, Prakhar, Mathew, Ribu, Beohar, Ankur |
Předmět: |
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Zdroj: |
IETE Journal of Research; Dec2023, Vol. 69 Issue 12, p9166-9173, 8p |
Abstrakt: |
The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
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