| Autor: |
Molinar-Solis, Jesus E., Sanchez-Arias, Daniel, Fajardo-Delgado, Daniel, Ocampo-Hidalgo, Juan J., Padilla-Cantoya, Ivan |
| Předmět: |
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| Zdroj: |
Journal of Circuits, Systems & Computers; 3/15/2024, Vol. 33 Issue 4, p1-17, 17p |
| Abstrakt: |
In this paper, the clamping effect introduced by several diode-based configurations used for the implementation of the high-value resistors in quasi-floating-gate circuits is analyzed and characterized. In contrast to previous approaches where a parasitic diode is treated as a simple high-value resistor reducing the circuit complexity, in this case the analysis considers the diode behavior which leads to a clamping circuit. This clamping circuit introduces an unwanted amplitude-dependent offset voltage, which affects the performance moving the quiescent point at the quasi-floating-gate transistors. A new anti-parallel diode configuration for quasi-floating-gate applications is proposed in this work, which eliminates this unwanted offset voltage. The proposed design is validated using simulations and experimental data in a CMOS 0.35- μ m technology. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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