| Autor: |
Praveen Kumar, S., Lingaraja, D., Gayathri, V. R., Ramya, S., Dinesh Ram, G., Aravind, T. |
| Předmět: |
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| Zdroj: |
AIP Conference Proceedings; 2024, Vol. 2935 Issue 1, p1-4, 4p |
| Abstrakt: |
The goal of the 10T memory cell's design is to allow it to bounce back from failure at any of the weak nodes. High stability, low power consumption, and a minimal environmental impact are important design priorities. The paper begins by proposing a 10T memory cell with appropriate transistor size and an upset physical mechanism to increase reliability in an aeronautical radiation environment. To show the efficacy of RHBD, we use Tanner Tool to stimulate the suggested idea in a TSMC 65nm CMOS process. The 10T memory cell architecture is more resilient to 0->1 and 1->0 single node upsets due to the longer read/write access time. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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