| Autor: |
M. A., Miroshnyk, S. I., Shmatkov, O. S., Shkil, А. М., Miroshnyk, K. Y., Pshenychnyi |
| Předmět: |
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| Zdroj: |
Radio Electronics, Computer Science, Control; 2023, Issue 4, p49-57, 9p |
| Abstrakt: |
Context. The issue of a synthesizable finite state machine with temporal events processing using hardware description language pattern. The object of this study is external event processing in real-time systems. Objective. The goal of this work is to introduce methods to express external temporal events on finite state machine state diagrams and corresponding HDL patterns of such events processing in control systems. Method. The classification of external events in real-time systems is analyzed. A device class that changes its internal state depending on the temporal external events is introduced. A method to express these events on the temporal state diagram is introduced. Possible model behavior scenarios based on the external event duration are analyzed. A Verilog HDL external event processing pattern is introduced. The efficiency of the proposed model is proved by developing, verifying, and synthesis of a powersaving module in Xilinx ISE. The results and testing showed the model's correctness. Results. External temporal events processing methods in real-time device models are proposed. The corresponding HDL pattern for the proposed model implementation is presented. Conclusions. The real-time systems with external temporal events automated synthesis problem has been solved. To solve this problem, a finite state machine model-based device using the Verilog language was developed and tested. The scientific novelty lies in the introduction a method to express temporal events on the state diagram of the finite state machine as well as in a HDL when implementing the proposed model on CPLD and FPGA. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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