| Autor: |
Schwantes, Stefan, Florian, Tobias, Stephan, Thilo, Graf, Michael, Dudek, Volker |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Electron Devices; Jul2005, Vol. 52 Issue 7, p1649-1655, 7p |
| Abstrakt: |
This paper discusses for the first time the impact of the back-gate bias on lateral DMOS (LDMOS) transistors on silicon-on-insulator (SOI) substrates. An analytical model that takes the back-gate bias and the device parameters into account is presented and verified with a 0.8-μm, 80-V SOI smart power technology. It will be explained that the effect of the back-gate bias on the LDPMOS devices is directly opposed to the LDnMOS transistors. The p-channel and the n-channel devices require different design strategies for the optimal buried oxide thickness due to the effect of the back-gate. A new device structure, namely body buried oxide step structure (BBOSS) that locally weakens the effect of the back-gate is presented. The proposed new structure allows a separated optimization of the buried oxide thickness without affecting the on-resistance. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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