Optimization of Side wall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/ Circuit Perspective.
| Autor: | Anguru, Chandana, Aryasomayajula, Vamsi Krishna, Kotha, Venkata Ramakrishna, Valasa, Sresta, Bhukya, Sunitha, Vadthiya, Narendar, Bheemudu, V., Kallepelli, Sagar, Maheshwaram, Satish, Mudidhe, Praveen Kumar |
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| Zdroj: | ECS Journal of Solid State Science & Technology; Jan2024, Vol. 13 Issue 1, p32-42, 11p |
| Databáze: | Complementary Index |
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