Autor: |
Thoti, Narasimhulu, Li, Yiming |
Zdroj: |
Applied Physics Express; Jan2024, Vol. 17 Issue 1, p1-5, 5p |
Abstrakt: |
The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET's device-level simulations are implemented and deliberated in strict compliance with the experimental settings. This work comprises the study of physical and DC analyses by scaling the p - to n -CTFET separation (D pn ), being a significant factor in CFET/CTFET design for its process difficulty. By utilizing the 50% benefit in footprint, the work is further extended to CTFET static random access memory implementation and characterization with hold/read noise margin analysis. [ABSTRACT FROM AUTHOR] |
Databáze: |
Complementary Index |
Externí odkaz: |
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