| Autor: |
Rajalingam, Prithiviraj, Srinivasan, Balaji, Jayakumar, Selvakumar, Routray, Soumyaranjan |
| Předmět: |
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| Zdroj: |
International Journal of Numerical Modelling; Jan2024, Vol. 37 Issue 1, p1-14, 14p |
| Abstrakt: |
The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was 103.2μW demonstrating the effectiveness of 10T PFD over other conventional PFDs. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
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