| Abstrakt: |
In this study, a 94 GHz PLL chip was designed using the integer-N PLL structure, and the results of a high-temperature test for the chip are discussed. The 94 GHz PLL was designed to exhibit a phase noise of −90 dBc/Hz or less at a 1 MHz offset frequency using a 0.13 μm SiGe BiCMOS process. In addition, a high-temperature test of the MIL-STD-331C standard was conducted on a manufactured 94 GHz SiGe PLL chip mounted on a test board. As a result of the test, the chip total current change before and after the high-temperature test was 4.7 %, and the phase noise changes of both 94 GHz VCO and PLL were 2.3 dB. These results confirm that, even after the high-temperature test, the flattening of the low-frequency noise was well maintained because the VCO noise was filtered by the PLL. [ABSTRACT FROM AUTHOR] |
