| Abstrakt: |
The Support Vector Machine (SVM) can be used to perform linear and nonlinear operations to solve regression and classification problems. The SVM algorithm is straightforward, generating a line or a hyperplane that can be used for separating different classes of data. However, due to its high computational complexity, SVM is a time-consuming algorithm when modeled solely with software. Various researchers attempted to implement SVM in hardware particularly on field-programmable gate array (FPGA) platforms in order to achieve high performance at lower cost and power consumption. As a result, the algorithm is unsuitable for embedded real-time applications. Therefore, SVM linear classifier is implemented on hardware which decreases the latency and executes the task in real time. In this paper, an SVM linear classifier with pipeline architecture is proposed for fast processing in Verilog HDL using a single-precision IEEE standard 754 number format. In order to perform a study related to hardware resource utilization and timing for the WBCD breast cancer datasets. The various performance metrics such as resource utilization, on-chip power consumption, and static timing analysis with constraints are evaluated. The accuracy rate is computed both using software and hardware for performance evaluation. The pipelined SVM architecture is designed using Verilog HDL, and then it is synthesized using the Vivado simulation tool. The design is configured to the Xilinx KC705 Kintex-7 evaluation board for implementation. This paper mainly focuses on the design of an SVM linear classifier with pipelined architecture for FPGA implementation. The FPGA-based two-class SVM classifier can perform fast data classification due to the advanced parallel calculation feature provided by FPGA. The classification system operates in a linear fashion. The simulation and synthesis results show that the SVM linear classification system can be able to classify data effectively. [ABSTRACT FROM AUTHOR] |
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